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Added note and refactor code #16

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PeterSurda merged 6 commits from swapnil/idlers-agent:main into main 2024-06-26 01:47:20 +02:00
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1 changed files with 2 additions and 3 deletions
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agent.py
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@ -163,7 +163,7 @@ class ServerData:
logging.info("Post data created") logging.info("Post data created")
return post_data return post_data
def create_note_data(self, server_id): def create_note_data(self):
chassis_info = None chassis_info = None
for section in self.dmidecode_data: for section in self.dmidecode_data:
if section['DMIType'] == 1: if section['DMIType'] == 1:
@ -183,7 +183,6 @@ class ServerData:
chassis_model, chassis_serial, processor_model, processor_count, '\n'.join(['R1', 'R2', 'R3'])) chassis_model, chassis_serial, processor_model, processor_count, '\n'.join(['R1', 'R2', 'R3']))
note_data = { note_data = {
'service_id': server_id,
'note': note, 'note': note,
} }
PeterSurda commented 2024-06-26 01:37:26 +02:00
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I was looking at some systems, and sometimes both TotalWidth and DataWidth is 72. I'm not really sure what it means. I vaguely remember reading that that's a bug in some DDR4 modules or motherboards. For now I would only check for TotalWidth and ignore DataWidth.

I was looking at some systems, and sometimes both TotalWidth and DataWidth is 72. I'm not really sure what it means. I vaguely remember reading that that's a bug in some DDR4 modules or motherboards. For now I would only check for TotalWidth and ignore DataWidth.
swapnil commented 2024-06-26 06:22:21 +02:00
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I did some reading on this. TotalWidth is DataWidth + (any extra bits for error correction). So it doesn't matter what the exact number of the TotalWidth is, at least in theory. However, common configuration for ECC memory is to have TotalWidth of 72 bits and a DataWidth of 64, giving extra 8 bits for error checking.

TLDR; to determine if a memory module is ECC or non-ECC, we should compare TotalWidth and DataWidth. if TotalWidth > DataWidth: true else false.

I did some reading on this. TotalWidth is DataWidth + (any extra bits for error correction). So it doesn't matter what the exact number of the TotalWidth is, at least in theory. However, common configuration for ECC memory is to have TotalWidth of 72 bits and a DataWidth of 64, giving extra 8 bits for error checking. TLDR; to determine if a memory module is ECC or non-ECC, we should compare TotalWidth and DataWidth. `if TotalWidth > DataWidth: true else false`.
PeterSurda commented 2024-06-27 00:57:12 +02:00
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It misreports on some DDR4 systems and I haven't found conclusive clarification. I have one system for example which reports TotalWidth 72 and DataWidth 72. But it doesn't influence the amount of available memory.

It misreports on some DDR4 systems and I haven't found conclusive clarification. I have one system for example which reports TotalWidth 72 and DataWidth 72. But it doesn't influence the amount of available memory.
return note_data return note_data
@ -298,7 +297,7 @@ def main():
server_id = server_manager.upsert_server(post_data) server_id = server_manager.upsert_server(post_data)
logging.info('Server id: {}'.format(server_id)) logging.info('Server id: {}'.format(server_id))
note_data = server_data.create_note_data(server_id) note_data = server_data.create_note_data()
server_manager.upsert_note(note_data, server_id) server_manager.upsert_note(note_data, server_id)
if __name__ == '__main__': if __name__ == '__main__':